SH7710 Datasheet, PDF (291/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
Bit
Bit Name Initial Value R/W Description
7

0
R
Reserved
6

0
5

0
R
These bits are always read as 0. The write value
R
should always be 0.
4

0
R
3

0
R
2

0
R
1

0
R
0

0
R
Note: * When NMI input is high, 0 when NMI input is low.
8.4.3 Interrupt Control Register 1 (ICR1)
ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ0 to
IRQ5 individually: rising edge, falling edge, high level, or low level. This register is initialized to
H′4000 by a power-on reset or manual reset, but is not initialized in standby mode.
Bit
Bit Name Initial Value R/W Description
15
MAI
0
R/W All Interrupt Mask
When this bit is set to 1, all interrupt requests
are masked while low level is input to the NMI
pin. In standby mode, an NMI interrupt is
masked.
0: When the NMI pin is low, all interrupt requests
are not masked
1: When the NMI pin is low, all interrupt requests
are masked
14
IRQLVL
1
R/W Interrupt Request Level Detection
Enables or disables the use of pins IRQ3 to
IRQ0 as four independent interrupt pins. The
IRQ4 and IRQ5 pins are not affected.
0: Use of pins IRQ3 to IRQ0 as four
independent interrupt pins enabled
1: Use of pins IRL3 to IRL0 as encoded 15 level
interrupt pins
Rev. 2.00 Dec. 07, 2005 Page 249 of 950
REJ09B0079-0200