SH7710 Datasheet, PDF (456/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Burst Read: A burst read occurs in the following cases with this LSI.
1. Access size in reading is larger than data bus width.
2. 16-byte transfer in cache miss.
3. 16-byte transfer in DMAC or E-DMAC (access to non-cachable area)
This LSI always accesses the SDRAM with burst length 1. For example, read access of burst
length 1 is performed consecutively 4 times to read 16-byte continuous data from the SDRAM that
is connected to a 32-bit data bus.
Table 12.18 shows the relationship between the access size and the number of bursts.
Table 12.18 Relationship between Access Size and Number of Bursts
Bus Width
16 bits
32 bits
Access Size
8 bits
16 bits
32 bits
16 bytes
8 bits
16 bits
32 bits
16 bytes
Number of Bursts
1
1
2
8
1
1
1
4
Figures 12.14 and 12.15 show a timing chart in burst read. In burst read, an ACTV command is
output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA
command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external
clock (CKIO) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an
auto-precharge induced by the READA command in the SDRAM. In the Tap cycle, a new
command will not be issued to the same bank. However, access to another CS space or another
bank in the same SDRAM space is enabled. The number of Tap cycles is specified by the TRP1
and TRP0 bits in CS3WCR.
In this LSI, wait cycles can be inserted by specifying each bit in CSnWCR to connect the SDRAM
in variable frequencies. Figure 12.15 shows an example in which wait cycles are inserted. The
number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where
the READA command is output can be specified using the TRCD1 and TRCD0 bits in CS3WCR.
If the TRCD1 and TRCD0 bits specify one cycle or more, a Trw cycle where the NOP command
is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles from the Tc1 cycle
Rev. 2.00 Dec. 07, 2005 Page 414 of 950
REJ09B0079-0200