SH7710 Datasheet, PDF (728/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
Initial
Bit Bit Name Value R/W Description
0
TEN31 0
R/W CAM Entry Table 31 (TSU_ADRH31 and TSU_ADRL31)
Setting
0: Disabled
1: Enabled
18.3.40 CAM Entry Table POST1 Register (TSU_POST1)
When using the CAM, the conditions for referring to each CAM entry table can be specified by
using the TSU_POST1 to TSU_POST4 registers. TSU_POST1 specifies the conditions for
referring to TSU_ADRH0 to TSU_ADRH7 and TSU_ADRL0 to TSU_ADRL7. The settings of
this register are valid when the POSENU bit in TSU_FWSLC is set to 1.
Initial
Bit
Bit Name Value R/W Description
31 to 28 POST03 to All 0
POST00
R/W These bits set the conditions for referring to the
CAM entry table 0. By setting multiple bits to 1,
multiple conditions can be selected.
POST03: The CAM entry table 0 is referred in port 0
reception.
POST02: The CAM entry table 0 is referred in port 0
to 1 relay.
POST01: The CAM entry table 0 is referred in port 1
reception.
POST00: The CAM entry table 0 is referred in port 1
to 0 relay.
27 to 24 POST13 to All 0
POST10
R/W These bits set the conditions for referring to the
CAM entry table 1. By setting multiple bits to 1,
multiple conditions can be selected.
POST13: The CAM entry table 1 is referred in port 0
reception.
POST12: The CAM entry table 1 is referred in port 0
to 1 relay.
POST11: The CAM entry table 1 is referred in port 1
reception.
POST10: The CAM entry table 1 is referred in port 1
to 0 relay.
Rev. 2.00 Dec. 07, 2005 Page 686 of 950
REJ09B0079-0200