SH7710 Datasheet, PDF (64/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 1 Overview and Pin Function
Classification Symbol
I/O
Bus control
WE0(BE0) O
RAS
O
CAS
O
CKE
O
IOIS16
I
DQMUU
O
DQMUL
O
DQMLU
O
DQMLL
O
REFOUT
O
WAIT
I
Direct memory DREQ0,
I
access controller _DREQ1
(DMAC)
DACK0,
O
DACK1
TEND0,
O
TEND1
Name
Function
Byte write
Indicates that bits 7 to 0 of the data
in the external memory or device are
being written.
RAS
Connects RAS pin during access to
the SDRAM.
CAS
Connects CAS pin during access to
the SDRAM.
CK enable
Connects CKE pin during access to
the SDRAM.
16-bit I/O
selection
Indicates 16-bit I/O for PCMCIA.
DQM
Selects D31 to D24 during access to
the SDRAM.
DQM
Selects D23 to D16 during access to
the SDRAM.
DQM
Selects D15 to D8 during access to
the SDRAM.
DQM
Selects D7 to D0 during access to
the SDRAM.
Refresh request Outputs the refresh request in
output
master mode or bus release.
Wait
Inserts a wait cycle into the bus
cycles during access to the external
space.
DMA-transfer
request
Input pin for external requests for
DMA transfer.
DMA-transfer
request accept
Output pin for request acceptance,
in response to external requests for
DMA transfer.
DMA-transfer
end output
Output pin for DMA transfer end
signal.
Rev. 2.00 Dec. 07, 2005 Page 22 of 950
REJ09B0079-0200