SH7710 Datasheet, PDF (330/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 User Break Controller
Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not
included in the condition)
The ASID check is not included.
A user break occurs after an instruction of address H'00000404 is executed or before
instructions of addresses H'00008010 to H'00008016 are executed.
• Register specifications
BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E,
BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000008, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B sequential mode
<Channel A>
Address: H'00037226, Address mask: H'00000000, ASID = H'80
Bus cycle: L bus/instruction fetch (before instruction execution)/read/word
<Channel B>
Address: H'0003722E, Address mask: H'00000000, ASID = H'70
Data:
H'00000000, Data mask: H'00000000
Bus cycle: L bus/instruction fetch (before instruction execution)/read/word
After an instruction with ASID = H’80 and address H'00037226 is executed, a user break
occurs before an instruction with ASID = H’70 and address H'0003722E is executed.
• Register specifications
BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BARB = H'00031415,
BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300000
Specified conditions: Channel A/channel B independent mode
<Channel A>
Address: H'00027128, Address mask: H'00000000
Bus cycle: L bus/instruction fetch (before instruction execution)/write/word
The ASID check is not included.
<Channel B>
Address: H'00031415, Address mask: H'00000000
Data:
H'00000000, Data mask: H'00000000
The ASID check is not included.
Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not
included in the condition)
Rev. 2.00 Dec. 07, 2005 Page 288 of 950
REJ09B0079-0200