SH7710 Datasheet, PDF (715/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.34 Relay Status Register (TSU_FWSR)
TSU_FWSR is a 32-bit readable/writable register that indicates the status during relay operations.
By setting the TSU status interrupt mask register (TSU_FWINMK), this status can be notified to
the CPU as an interrupt source. The status bit set to 1 will be cleared to 0 by writing 1 to
corresponding bit. (The status bit retains the value until it is cleared to 0.)
Interrupts generated due to this status register is EINT2. For details on the priority order of
interrupts, refer to section 8.3.5, Interrupt Exception Handling and Priority in section 8, Interrupt
Controller (INTC).
Initial
Bit
Bit Name Value
31 to 28 
All 0
27
TINT40 0
26
TINT30 0
25
TINT20 0
24
TINT10 0
23
OVF0
0
22
RBSY0 0
21

0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W MAC-0 Carrier Not Detect
Set to 1 when a carrier not detect has occured in the
MAC-0
R/W MAC-0 Carrier Lost
Set to 1 when a carrier is lost during data transmission
in the MAC-0
R/W MAC-0 Collision Detect
Set to 1 when a collision of frames is detected in the
MAC-0
R/W MAC-0 Transmission Time Out
Set to 1 when frames were unable to be transmitted in
16 transmission attempts including the retransfer in the
MAC-0
R/W Port 0 to 1 TSU FIFO Overflow Detect
Set to 1 when a port 0 to 1 TSU FIFO overflow has
occured
R/W MAC-0 Overflow Alert Signal Output
Set to 1 when the threshold of TSU_BSYSL0 is valid
and exceeded
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Dec. 07, 2005 Page 673 of 950
REJ09B0079-0200