SH7710 Datasheet, PDF (43/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 1 Overview and Pin Function
Section 1 Overview and Pin Function
This LSI is a 32-bit reduced instruction set computer (RISC) microprocessor that is built on the
SuperH architecture.
Its core is a RISC-type CPU with a Digital Signal Processor (DSP) as a functional extension. A
single chip microprocessor integrates peripheral functions required for building an Ethernet
system.
The LSI comprises two channels of Ethernet controllers. They include a media access controller
(MAC) and a media independent interface (MII) standard unit that conforms to the IEE802.3u
standard and provide 10/100 Mbps LAN connection. The on-chip IP security accelerator enables
efficient security management of network data.
The LSI has a large capacity (32-kbyte) cache memory, 16-kbyte on-chip X/Y memory, and an
interrupt controller for system configuration to enable flexible system design. It supports high-
speed data transfer using an on-chip direct memory access controller (DMAC). Its external
memory access support provides direct connection to various types of memory.
The strong on-chip power saving function reduces power consumption even during high-speed
operation.
1.1 Features
The features of this LSI are shown below.
CPU:
• Original Renesas-Technology SuperH architecture
• Compatible with SH-1, SH-2, and SH-3 at object code level
• 32-bit internal data bus
• Various groups of built-in registers
General registers: Sixteen 32-bit registers (including eight 32-bit bank registers)
Control registers: Five 32-bit registers
System registers: Four 32-bit registers
• Supports RISC-type instruction set
Instruction length: 16-bit fixed length for improved code efficiency
Load/store architecture
Delayed branch instructions
Instruction set based on C language
• Instruction execution time: one instruction/cycle for basic instructions
Rev. 2.00 Dec. 07, 2005 Page 1 of 950
REJ09B0079-0200