SH7710 Datasheet, PDF (171/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
Arithmetic Shift: Figure 3.17 shows the arithmetic shift operation flow.
39 32 31
Left shift
16 15
0
0
Shift out
39
Shift amount data
(source 2)
>=0
<0
32 31
+32- -32
23 22 16 15
Sy
60
Imm1
39 32 31
(MSB copy)
Updated
0
Right shift
16 15
0
Shift out
DSR
GT Z N V DC
Ignored
Figure 3.17 Arithmetic Shift Operation Flow
Note:
The arithmetic shift operations are basically 40-bit operation, that is, the 32 bits of the
base precision and eight bits of the guard-bit parts. So the signed bit is copied to the guard-
bit parts when a register not providing the guard-bit parts is specified as the source
operand. When a register not providing the guard-bit parts is specified as a destination
operand, the lower 32 bits of the operation result are input into the destination register.
In this arithmetic shift operation, all bits of the source 1 and destination operands are activated.
The shift amount is specified by the source 2 operand as an integer data. The source 2 operand can
be specified by either a register or immediate operand. The available shift range is from –32 to
+32. Here, a negative value means the right shift, and a positive value means the left shift. It is
possible for any source 2 operand to specify from –64 to +63 but the result is unknown if an
invalid shift value is specified. In case of a shift with an immediate operand instruction, the source
1 operand must be the same register as the destination’s. This operation is executed in the DSP
stage, as shown in figure 3.10 as well as in fixed-point operations. The DSP stage is the same
stage as the MA stage in which memory access is performed.
Every time an arithmetic shift operation is executed, the DC, N, Z, V, and GT bits in DSR are
basically updated in accordance with the operation result. In case of a conditional operation, they
are not updated even though the specified condition is true and the operation is executed. In case
of an unconditional operation, they are always updated in accordance with the operation result.
The definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The DC
bit result is:
1. Carry or Borrow Mode: CS[2:0] = 000
The DC bit indicates the last shifted out data as the operation result.
2. Negative Value Mode: CS[2:0] = 001
Rev. 2.00 Dec. 07, 2005 Page 129 of 950
REJ09B0079-0200