SH7710 Datasheet, PDF (769/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Section 19 Ethernet Controller Direct Memory Access
Controller (E-DMAC)
This LSI has an on-chip two-channel direct memory access controller (E-DMAC0/1) directly
connected to the Ethernet controller (EtherC). By using the DMAC contained in the E-DMAC, the
E-DMAC transfers transmit/receive data between the transmit/receive FIFO in the E-DMAC and a
user-specified data storage destination (buffer) by DMA transfer. At DMA transfer, information
referenced by the E-DMAC is referred to as a transmit/receive descriptor, and the user places this
descriptor in memory.
This function reduces the load on the CPU and enables efficient data transfer control to be
achieved. The E-DMAC0 and E-DMAC1 control the data transmission/reception from the MAC-0
and MAC-1 of EtherC respectively. (Hereafter the channel controlled by the E-DMAC0 is channel
0. The channel controlled by the E-DMAC1 is channel 1.)
Figure 19.1 shows the configuration of the E-DMAC, and the descriptors and transmit/receive
buffers in memory.
19.1 Features
The E-DMAC has the following features:
• Contains two-channel independent transmit/receive DMAC
• The load on the CPU is reduced by means of a descriptor management system
• Transmit/receive frame status information is indicated in descriptors
• Achieves efficient system bus utilization through the use of DMA block transfer (16-byte
units)
• Supports single-frame/single-descriptor operation and single-frame/multi-frame (multi-buffer)
operation
Note: The E-DMAC cannot access peripheral modules.
EDMAS20B_000020020900
Rev. 2.00 Dec. 07, 2005 Page 727 of 950
REJ09B0079-0200