SH7710 Datasheet, PDF (643/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
17.3.7 SIOF FIFO Control Register (SIFCTR)
SIFCTR is used to indicate the area available for the transmit/receive FIFO transfer. SIFCTR is
initialized by a power-on reset or software reset.
Initial
Bit Bit Name Value R/W Description
15 TFWM2 0
R/W Transmit FIFO Watermark
14 TFWM1 0
13 TFWM0 0
R/W A transfer request to the transmit FIFO is issued by the TDREQ
R/W ^{bit in SISTR. The transmit FIFO is always used as 16 stages of}
FIFO regardless of these bit settings.
000: Issue a transfer request when 16 stages of transmit FIFO
are empty.
001: Reserved (setting prohibited)
010: Reserved (setting prohibited)
011: Reserved (setting prohibited)
100: Issue a transfer request when 12 or more stages of
transmit FIFO are empty.
101: Issue a transfer request when 8 or more stages of
transmit FIFO are empty.
110: Issue a transfer request when 4 or more stages of
transmit FIFO are empty.
111: Issue a transfer request when 1 or more stages of
transmit FIFO are empty.
12 TFUA4 1
R
Transmit FIFO Usable Area
11 TFUA3 0
10 TFUA2 0
R
Indicate the number of words that can be transferred by the
R
CPU or DMAC as B′00000 to B′10000.
9 TFUA1 0
R
8 TFUA0 0
R
Rev. 2.00 Dec. 07, 2005 Page 601 of 950
REJ09B0079-0200