SH7710 Datasheet, PDF (979/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Page Revision (See Manual for Details)
Table 12.15 Relationship between 408
A2/3BSZ[1:0], A2/3ROW[1:0],
A2/3COL[1:0], and Address
Multiplex Output (4)-1
Output Pin
of This LSI
Row
Address
Output
A17
A25
A16
A24
A15
A23
A14
A22
A13
A21
A12
A20*2
Column
Address
Output
Synchronous
DRAM Pin Function
A17
Unused
A16
A15
A14
A21
A20*²
A11 (BA0)
Specifies
bank
Burst Read:
1. Auto-refreshing
Figure 12.38 Example of
PCMCIA Interface Connection
414 In this LSI, wait cycles can be inserted by specifying
each bit in CSnWCR to connect the SDRAM in variable
frequencies. Figure 12.15 shows an example in which
wait cycles are inserted. The number of cycles from
the Tr cycle where the ACTV command is output to the
Tc1 cycle where the READA command is output can be
specified using the TRCD1 and TRCD0 bits in
CS3WCR. If the TRCD1 and TRCD0 bits specify one
cycle or more, a Trw cycle where the NOP command is
issued is inserted between the Tr cycle and Tc1 cycle.
428 A NOP cycle is inserted between the Tp cycle and Trr
cycle when the setting value of the TRP[1:0] bits in
CSnWCR is longer than or equal to 1 cycle.
447
This LSI
A25 to A0
D7 to D0
D15 to D8
RD/WR
CE1A
CE2A
RD
PC card
(memory I/O)
G
A25 to A0
D7 to D0
G
DIR
D15 to D8
G
DIR
CE1
CE2
OE
WE/PGM
Rev. 2.00 Dec. 07, 2005 Page 937 of 950
REJ09B0079-0200