SH7710 Datasheet, PDF (795/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.2.19 Transmit Interrupt Register (TRIMD)
TRIMD is a 32-bit readable/writable register that specifies whether or not to notify write-back
completion for each frame using the TWB bit in EESR and an interrupt on transmit operations.
Initial
Bit
Bit Name Value R/W Description
31 to 1 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
TIS
0
R/W Transmit Interrupt Setting
0: Write-backed completion for each frame using the
TWB bit in EESR is notified
1: Write-back completion for each frame is not
notified
19.3 Operation
Using its direct memory access (DMA) function, the E-DMAC performs DMA transfer of
transmit/receive data between a Ethernet frame transmission/reception data storage destination of
user- specified (accessible memory space: transmit buffer/receive buffer) and the transmit/receive
FIFO in the E-DMAC. (The user cannot read and write data in the transmit/receive FIFO directly
via the CPU).
To enable the E-DMAC to perform DMA transfer, information (data) including a transmit/receive
data storage address and so forth, referred to as a descriptor, is required. Before Ethernet frame
transmission/reception, the E-DMAC reads descriptor information, then reads transmit data from
the transmit buffer or writes receive data to the receive buffer according to the read descriptor
information. By arranging multiple descriptors as a descriptor row (list) (to be placed in a
readable/writable memory space), multiple Ethernet frames can be transmitted or received
continuously.
Rev. 2.00 Dec. 07, 2005 Page 753 of 950
REJ09B0079-0200