SH7710 Datasheet, PDF (977/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
• CS3WCR
Page Revision (See Manual for Details)
370
Bit
4
3
1
0
Bit
Name Description
TRWL1 Number of Wait Cycles Waiting Start of
TRWL0 Precharge Specify the number of minimum wait
cycles to be inserted to wait the start of
precharge. The setting for areas 2 and 3 is
common.
(1) This LSI is in non-bank active mode from the
issue of the WRITA command to the start of
auto-precharge in SDRAM, and issues the
ACTV command for the same bank after
issuing the WRITA command. Confirm how
many cycles are required from the reception
of the WRITA command to the start of auto-
precharge in each SDRAM data sheet. Set
this bit so that the number of cycles is not
above the cycles specified by this bit.
(2) This LSI is in bank active mode from issuing
the WRIT command to issuing the PRE
command, and the access to different row
address in the same bank is performed.
00: 0 cycle (No wait cycle)
01: 1 cycle
10: 2 cycles
11: 3 cycles
TRC1
TRC0
Number of Idle Cycles from REF Command/Self-
refresh Release to ACTV/REF/MRS Command
Specify the number of minimum idle cycles
between the commands in the following cases.
The setting for areas 2 and 3 is common.
(1) From issuing the REF command to issuing the
ACTV/REF/MSR command
(2) From releasing self-refresh to issuing the
ACTV/REF/MSR command
00: 2 cycles
01: 3 cycles
10: 5 cycles
11: 8 cycles
Rev. 2.00 Dec. 07, 2005 Page 935 of 950
REJ09B0079-0200