SH7710 Datasheet, PDF (806/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name Value R/W Description
29
RFP1
0
R/W Receive Frame Position 1, 0
28
RFP0
0
R/W The E-DMAC indicates by write-back operation
whether information of the corresponding descriptor
represents information about the start, middle, or end
of the receive frame.
00: The information of the descriptor represents
information about the middle of the frame.
01: The information of the descriptor represents
information about the end of the frame.
10: The information of the descriptor represents
information about the start of the frame.
11: The information of the descriptor represents all
information about the frame (single-frame/single-
descriptor (single-buffer)).
Reference:
The relationship between a frame after reception of
one frame and a descriptor is described below.
[For single-frame/single-descriptor operation]
First descriptor: RFP[1:0] = 11
[For single-frame/two-descriptor operation]
First descriptor: RFP[1:0] = 10
Second descriptor: RFP[1:0] = 01
[For single-frame/three-descriptor operation]
First descriptor: RFP[1:0] = 10
Second descriptor: RFP[1:0] = 00
Third descriptor: RFP[1:0] = 01
When the number of divisions is large, a descriptor
row is configured by adding intermediate descriptors
with RFP[1:0] = 00.
Rev. 2.00 Dec. 07, 2005 Page 764 of 950
REJ09B0079-0200