SH7710 Datasheet, PDF (814/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
(2) Receive Processing in Case of Multi-Buffer Frame
If an error occurs during reception in the case of a multi-buffer frame where a receive frame is
divided for storage in multiple buffers, the E-DMAC performs the processing shown in figure
19.7.
In the figure, the invalid receive descriptors (with the RACT bit cleared to 0) represent the normal
reception of data to be stored in buffers, and the valid receive descriptors (with the RACT bit set
to 1) represent unreceived buffers. If a frame receive error occurs with a descriptor shown in the
figure, the status is written back to the corresponding descriptor.
If error interrupts are enabled in the EtherC/E-DMAC status interrupt permission register
(EESIPR), an interrupt is generated immediately after the write-back. If there is a new frame
receive request, reception is continued from the buffer after that in which the error occurred.
Descritptors
E-DMAC
.
.
.
.
.
.
.
.
Inactivates RACT and writes RFE, RFS
Descriptor read
RR
AD
CL
TE
00
00
00
10
10
RR
FF
PP
10
10
Frame
type
Start
0 0 Continue
0 0 Continue
00
00
10 00
10 00
10 00
11 00
Start of frame
Receive error
occurrence
New frame reception
continues from this buffer
Buffer length set
by descriptor
Figure 19.7 E-DMAC Operation after Receive Error
Received data
Unreceived data
Rev. 2.00 Dec. 07, 2005 Page 772 of 950
REJ09B0079-0200