SH7710 Datasheet, PDF (642/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
0
RXRST 0
R/W Reception Reset
This bit setting becomes valid immediately. When the 1
setting for this bit becomes valid, the SIOF immediately
disables reception from the RXD_SIO pin, and initializes
the reception data register and reception-related status
register. The following are initialized.
• SIRDR
• Receive FIFO write/read pointer
• RCRDY, RFFUL, and RDREQ bits in SISTR
• RXE bit
As the SIOF is cleared automatically at the completion of
reset operation, this bit is always read as 0.
0: Reception operation is not reset
1: Resets reception operation
Rev. 2.00 Dec. 07, 2005 Page 600 of 950
REJ09B0079-0200