SH7710 Datasheet, PDF (777/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name Value R/W Description
30
TWB
0
R/W Write-Back Complete
Indicates that write-back from the E-DMAC to the
corresponding descriptor has completed. This
operation is enabled when the TIS bit in TRIMD is set
to 1.
0: Write-back has not completed, or no transmission
directive
1: Write-back has completed
29 to 27 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
26
TABT
0
R/W Transmit Abort Detection
Indicates that the EtherC aborts transmitting a frame
because of failures during transmitting the frame.
0: Frame transmission has not been aborted or no
transmit directive
1: Frame transmit has been aborted
25
RABT
0
R/W Receive Abort Detection
Indicates that the EtherC aborts receiving a frame
because of failures during receiving the frame.
0: Frame reception has not been aborted or no
receive directive
1: Frame receive has been aborted
24
RFCOF
0
R/W Receive Frame Counter Overflow
Indicates that the receive FIFO frame counter has
overflowed.
0: Receive frame counter has not overflowed
1: Receive frame counter overflows
Rev. 2.00 Dec. 07, 2005 Page 735 of 950
REJ09B0079-0200