SH7710 Datasheet, PDF (688/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
Initial
Bit
Bit Name Value
R/W Description
9
MPDE 0
R/W Magic Packet Detection Enable
Enables or disables Magic Packet detection by
hardware to allow activation from the Ethernet.
0: Magic Packet detection is not enabled
1: Magic Packet detection is enabled
8

0
R
Reserved
7

0
R
These bits are always read as 0. The write value
should always be 0.
6
RE
0
R/W Reception Enable
If a switch is made from receive function enabled (RE
= 1) to disabled (RE = 0) while a frame is being
received, the receive function will be enabled until
reception of the corresponding frame is completed.
0: Receive function is disabled
1: Receive function is enabled
5
TE
0
R/W Transmission Enable
If a switch is made from transmit function enabled
(TE = 1) to disabled (TE = 0) while a frame is being
transmitted, the transmit function will be enabled until
transmission of the corresponding frame is
completed.
0: Transmit function is disabled
1: Transmit function is enabled
4

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
3
ILB
0
R/W Internal Loop Back Mode
Specifies loopback mode in the EtherC.
0: Normal data transmission/reception is performed.
1: Data loopback is performed inside the MAC in the
EtherC.
Rev. 2.00 Dec. 07, 2005 Page 646 of 950
REJ09B0079-0200