SH7710 Datasheet, PDF (690/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.3 EtherC Status Register (ECSR)
ECSR is a 32-bit readable/writable register and indicates the status in the EtherC. This status can
be notified to the CPU by interrupts. When 1 is written to the BRCRX, PSRTO, LCHNG, MPD,
and ICD, the corresponding flags can be cleared. Writing 0 does not affect the flag. For bits that
generate interrupt, the interrupt can be enabled or disabled according to the corresponding bit in
ECSIPR.
The interrupts generated due to this status register are indicated in each ECI bit in EESR of the E-
DMAC0 derived from port0 and the E-DMAC1 derived from port1.
Bit
Bit Name
31 to 3 
Initial
Value
All 0
2
LCHNG 0
1
MPD
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Link Signal Change
Indicates that the LNKSTA signal input from the PHY-
LSI has changed from high to low or low to high.
However, signal changes may be detected at the timing
at which the LNKSTA function was selected using
PACR of PFC.
To check the current Link state, refer to the LMON bit in
the PHY status register (PSR).
0: Change in the LNKSTA signal has not been detected
1: Change in the LNKSTA signal has been detected
(high to low or low to high)
R/W Magic Packet Detection
Indicates that a Magic Packet has been detected on the
line.
0: Magic Packet has not been detected
1: Magic Packet has been detected
Rev. 2.00 Dec. 07, 2005 Page 648 of 950
REJ09B0079-0200