SH7710 Datasheet, PDF (583/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.6 Serial Control Register (SCSCR)
SCSCR performs enabling or disabling of the SCIF transfer operations and interrupt requests, and
selection of the serial clock source.
SCSCR can be read or written to by the CPU at all times.
SCSCR is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby
mode or in the module standby state, and retains its contents.
Initial
Bit
Bit Name Value R/W Description
15 to 8 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
7
TIE
0
R/W Transmit Interrupt Enable
Enables or disables generation of a transmit-FIFO-
data-empty interrupt (TXI) request when the TDFE
flag in SCFSR is set to 1 after the serial transmit data
is transferred from SCFTDR to SCTSR and the
number of data bytes in the transmit FIFO register is
equal to or below the trigger set number.
0: Transmit-FIFO-data-empty interrupt (TXI) request
disabled*
1: Transmit-FIFO-data-empty interrupt (TXI) request
enabled
Note: *
TXI interrupt requests can be cleared by
writing transmit data exceeding the transmit
trigger set number to SCFTDR, reading 1
from the TDFE flag, then clearing it to 0, or
by clearing the TIE bit to 0.
Rev. 2.00 Dec. 07, 2005 Page 541 of 950
REJ09B0079-0200