SH7710 Datasheet, PDF (386/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
4

1
R
Reserved
This bit is always read as 1. The write value should always
be 1.
3
ENDIAN 0/1* R
Endian Flag
Samples the external pin for specifying endian on power-on
reset (MD5). All address spaces are defined by this bit.
This is a read-only bit.
0: The external pin for specifying endian (MD5) was low
level on power-on reset. This LSI is being operated as
big endian.
1: The external pin for specifying endian (MD5) was high
level on power-on reset. This LSI is being operated as
little endian.
2
CK2DRV 0
R/W CKIO2 Drive
Specifies whether the CKIO2 pin outputs a low level signal
or clock (Bφ).
0: Outputs a low level signal
1: Outputs a clock (Bφ)
1
HIZMEM 0
R/W High-Z Memory Control
Specifies the pin state in standby mode for A25 to A0, BS,
CSn, RD/WR, WEn (BEn)/DQMxx, and RD. When a bus is
released, these pins enter the high-impedance state
regardless of the setting of this bit.
0: High impedance in standby mode
1: Driven in standby mode
0
HIZCNT 0
R/W High-Z Control
Specifies the state in standby mode and bus released for
CKIO, CKIO2, CKE, RAS, and CAS.
0: High impedance in standby mode and bus released for
CKIO, CKIO2, CKE, RAS, and CAS.
1: Driven in standby mode and bus released for CKIO,
CKIO2, CKE, RAS, and CAS.
Note: If one of clock operating modes 4 to 6 is set, CKIO,
CKIO2, CKE, RAS, and CAS should be driven in
standby mode and bus released.
Note: * The external pin (MD5) for specifying endian is sampled on power-on reset. When big
endian is specified, this bit is read as 0 and when little endian is specified, this bit is
read as 1.
Rev. 2.00 Dec. 07, 2005 Page 344 of 950
REJ09B0079-0200