SH7710 Datasheet, PDF (338/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 10 Power-Down Modes
Table 10.1 States of Power-Down Modes
State
Mode
Transition
Conditions
CPG
CPU On-
On-Chip
EtherC
Reg- Chip Periphera
External Canceling
E-DMAC CPU ister Memory l Modules Pins Memory Procedure
Sleep
mode
Execute SLEEP Run
instruction with
STBY bit cleared
to 0 in STBCR
Software Execute SLEEP Halt
Standby instruction with
mode STBY bit set to 1
in STBCR
Module
standby
function
Set MSTP bit to 1 Run
in STBCR,
STBCR2, and
STBCR3
Halt Held Held
Halt Held Held
Run Held Held
Run
Held Refreshe 1. Interrupt
d
2. Reset
Halt*¹
Held Self-
1. Interrupt
refreshed _{2. Reset}
Specified *²
module
halts
Refreshe 1. Clear
d
MSTP
bit to 0
2. Power-
on reset
Notes: 1. The RTC runs when the START bit in RCR2 is set to 1. For details, see section 15,
Realtime Clock (RTC).
2. Depends on the on-chip peripheral modules. For details, see section 1, Overview and
Pin Function.
10.1.2 Reset
A reset is used at power-on or to re-execute from the initial state. This LSI supports two types of
reset: power-on reset and manual reset. In power-on reset, any processing to be currently executed
is terminated and any events not executed are canceled to execute reset processing immediately. In
manual reset, processing required to maintain external memory contents is continued. The
following shows the conditions in which power-on reset or manual reset occurs.
• Power-on reset
1. A low level signal is input to the RESETP pin.
2. The WDT counter overflows if the WDT starts counting while the WT/IT and RSTS bits in
WTCSR are set to 1 and cleared to 0, respectively.
3. An H-UDI reset occurs. (For details on the H-UDI reset, refer to section 23, User
Debugging Interface (H-UDI).)
Rev. 2.00 Dec. 07, 2005 Page 296 of 950
REJ09B0079-0200