SH7710 Datasheet, PDF (473/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
CKIO
CKE
A25 to A0
A12/A11*¹
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*²
Tp
Tpw
Trr
Trc
Hi-z
Trc
Trc
Trc
Trc
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 12.26 Self-Refresh Timing
Relationship between Refresh Requests and Bus Cycles: If a refresh request occurs during bus
cycle execution, the refresh cycle must wait for the bus cycle to be completed. If a refresh request
occurs while the bus is released by the bus arbitration function, the refresh will not be executed
until the bus mastership is acquired. This LSI supports requests by the REFOUT pin for the bus
mastership while waiting for the refresh request. The REFOUT pin is asserted low until the bus
mastership is acquired.
If a new refresh request occurs while waiting for the previous refresh request, the previous refresh
request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the bus
mastership occupation must be prevented from occurring. If a bus mastership is requested during
self-refresh, the bus will not be released until the self-refresh is completed.
Low-Frequency Mode: When the SLOW bit in SDCR is set to 1, output of commands, addresses,
and write data, and fetch of read data are performed at a timing suitable for operating SDRAM at a
low frequency.
Rev. 2.00 Dec. 07, 2005 Page 431 of 950
REJ09B0079-0200