SH7710 Datasheet, PDF (848/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 23 User Debugging Interface (H-UDI)
TCK
TDO
(when the H-UDI
command is set)
TDO
(when the JTAG
command is set)
t_TDO
t_TDO
Figure 23.3 H-UDI Data Transfer Timing
23.4.4 H-UDI Reset
An H-UDI reset is executed by inputting an H-UDI reset assert command in SDIR. An H-UDI
reset is of the same kind as a power-on reset. An H-UDI reset is released by inputting an H-UDI
reset negate command. The required time between the H-UDI reset assert command and H-UDI
reset negate command is the same as time for keeping the RESETP pin low to apply a power-on
reset.
SDIR
H-UDI reset assert
H-UDI reset negate
Chip internal reset
CPU state
Branch to H'A0000000
Figure 23.4 H-UDI Reset
23.4.5 H-UDI Interrupt
The H-UDI interrupt function generates an interrupt by setting a command from the H-UDI in the
SDIR. An H-UDI interrupt is a general exception/interrupt operation, resulting in a branch to an
address based on the VBR value plus offset, and with return by the RTE instruction. This interrupt
request has a fixed priority level of 15.
H-UDI interrupts are accepted in sleep mode.
Rev. 2.00 Dec. 07, 2005 Page 806 of 950
REJ09B0079-0200