SH7710 Datasheet, PDF (946/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 25 Electrical Characteristics
SCIFnCK
TxD
(data trans-
mission)
RxD
(data
reception)
RTS
CTS
t_Scyc
t_TXD
t_RTSD
t_RXS t_RXH
t_CTSS t_CTSH
Figure 25.52 SCIF Input/Output Timing in Clock Synchronous Mode
25.3.10 SIOF Module Signal Timing
Table 25.12 SIOF Module Signal Timing
Item
(Conditions: V Q = V Q-RTC = 3.0 to 3.6 V, V = V -PLL1 = V -PLL2 = 1.4 to 1.6 V,
CC
CC
CC
CC
CC
V Q = V = V Q-RTC = V -PLL1 = V -PLL2 = 0 V, T = –20 to 75°C)
SS
SS
SS
SS
SS
a
Symbol Min.
Max. Unit Figure
SIOMCLK clock input cycle time t
30
—
Mcyc
SIOMCLK input high-level width t
MWH
0.4
×
t
Mcyc
—
SIOMCLK input low-level width
t
MWL
0.4
×
t
Mcyc
—
SCK_SIO clock cycle time
t
SIcyc
2
×
t
Pcyc
—
SCK_SIO output high-level width t_SWHO
0.4 × t_SIcyc
—
SCK_SIO output low-level width
t_SWLO
0.4 × t_SIcyc
—
SIOFSYNC output delay time
t_FSD
—
20
SCK_SIO input high-level width
t_SWHI
0.4 × t_SIcyc
—
SCK_SIO input low-level width
t
SWLI
0.4
×
t
SIcyc
—
SIOFSYNC input setup time
t
20
—
FSS
SIOFSYNC input hold time
t
20
—
FSH
TXD_SIO output delay time
t
—
20
STDD
RXD_SIO input setup time
t
20
—
SRDS
RXD_SIO input hold time
t_SRDH
20
—
Note: t_Pcyc is the cycle time (ns) of the peripheral clock (Pφ).
ns 25.53
25.54 to 25.58
25.54 to 25.57
25.58
25.54 to 25.58
Rev. 2.00 Dec. 07, 2005 Page 904 of 950
REJ09B0079-0200