SH7710 Datasheet, PDF (420/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
12
SLOW 0
R/W Low-Frequency Mode
Specifies the output timing of command, address, and write
data for SDRAM and the latch timing of read data from
SDRAM. Setting this bit makes the hold time for command,
address, write and read data extended for half cycle (output
or read at the falling edge of CKIO). When this bit set to 1,
the hold time for command, address, and write and read
data can be extended. This mode is suitable for SDRAM
with low-frequency clock.
0: Command, address, and write data for SDRAM is output
at the rising edge of CKIO. Read data from SDRAM is
latched at the rising edge of CKIO.
1: Command, address, and write data for SDRAM is output
at the falling edge of CKIO. Read data from SDRAM is
latched at the falling edge of CKIO.
11
RFSH 0
R/W Refresh Control
Specifies whether or not the refresh operation of the
SDRAM is performed.
0: No refresh
1: Refresh
10
RMODE 0
R/W Refresh Control
Specifies whether to perform auto-refresh or self-refresh
when the RFSH bit is 1. When the RFSH bit is 1 and this bit
is 1, self-refresh starts immediately. When the RFSH bit is 1
and this bit is 0, auto-refresh starts according to the
contents that are set in RTCSR, RTCNT, and RTCOR.
0: Auto-refresh is performed
1: Self-refresh is performed
9
PDOWN 0
R/W Power-Down Mode
Specify whether SDRAM is put in power-down mode or not
after the access to memory other than SDRAM is
completed. This bit, when set to 1, drives the CKE pin low
and places SDRAM in power-down mode by using an
access to a memory other than SDRAM as a trigger.
0: Does not place SDRAM in power-down mode after an
access to a memory other than SDRAM.
1: Places SDRAM in power-down mode after an access to a
memory other than SDRAM.
Rev. 2.00 Dec. 07, 2005 Page 378 of 950
REJ09B0079-0200