SH7710 Datasheet, PDF (558/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 15 Realtime Clock (RTC)
Bit
7
6
5, 4
3 to 0
Bit Name
ENB
Initial Value R/W
0
R/W

0
R


R/W


R/W
Description
Hour Alarm Enable
Specifies whether comparison of RHRCNT and
RHRAR is performed as an alarm condition.
0: Not compared
1: Compared
Reserved
This bit is always read as 0. The write value
should always be 0.
Setting value for 10-unit of hour alarm in the
BCD-code.
The range can be set from 0 to 2 (decimal).
Setting value for 1-unit of hour alarm in the BCD-
code.
The range can be set from 0 to 9 (decimal).
15.3.12 Day of Week Alarm Register (RWKAR)
RWKAR is an alarm register corresponding to the day of week counter RWKCNT. When the
ENB bit is set to 1, a comparison with the RWKCNT value is performed. From among
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR, the counter and alarm register
comparison is performed only on those with ENB bits and the YAEN bit in RCR3 set to 1, and if
each of those coincide, an RTC alarm interrupt is generated.
The range of day of the week alarm which can be set is 0 to 6 (decimal). Errant operation will
result if any other value is set.
RWKAR is an 8-bit readable/writable register. The ENB bit in RWKAR is initialized by a power-
on reset. The remaining RWKAR fields are not initialized by a power-on reset or manual reset, or
in standby mode.
Rev. 2.00 Dec. 07, 2005 Page 516 of 950
REJ09B0079-0200