SH7710 Datasheet, PDF (382/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
12.3.4 Area 0 Memory Type and Memory Bus Width
The memory bus width in this LSI can be set for each area. In area 0, external pins can be used to
select byte (8 bits), word (16 bits), or longword (32 bits) on power-on reset. The memory bus
width of the other area is set by the register. The correspondence between the memory type,
external pins (MD3, MD4), and bus width is listed in the table below.
Table 12.4 Correspondence between External Pins (MD3 and MD4), Memory Type of CS0,
and Memory Bus Width
MD4
MD3
Memory Type
Bus Width
0
0
Normal memory
Reserved (Setting prohibited)
1
8 bits*
1
0
16 bits
1
32 bits
Note: * The bus width must not be specified as eight bits if the burst ROM (clock synchronous)
interface is selected.
12.3.5 Data Alignment
This LSI supports the big endian and little endian methods of data alignment. The data alignment
is specified using the external pin (MD5) at power-on reset as shown in table 12.5.
Table 12.5 Correspondence between External Pin (MD5) and Endians
MD5
0
1
Endian
Big endian
Little endian
Rev. 2.00 Dec. 07, 2005 Page 340 of 950
REJ09B0079-0200