SH7710 Datasheet, PDF (749/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
EDMAC-0
CAMSEN pin
EDMAC-1
EtherC
TSU
CAM control
CAM
reference
CAM entry table
(32 entries × 48 bits)
External
CAM I/F
CAM
reference
(Reference setting:
TSU_TEN and TSU_FWSLC)
Relay
enable
TSU_FWEN1
Determination
of priority
TSU_PRISL0
CAM
reference
TSU FIFO
(1 to 0)
TSU FIFO
(0 to 1)
CAM
reference
Determination
of priority
TSU_PRISL1
Relay enable
TSU_FWEN0
Transmission
enable
TE (ECMR0) = 1
Reception
enable
RE (ECMR0) = 1
Reception
enable
RE (ECMR1) = 1
Transmission
enable
TE (ECMR1) = 1
MAC-0
MAC-1
PHY-0
PHY-1
Figure 18.2 EtherC Data Path and Various Settings
18.4.1 Transmission
The EtherC transmitter assembles the transmit data on the frame and outputs to MII when there is
a transmit request from the E-DMAC. The data transmitted via the MII is transmitted to the lines
by PHY-LSI. Figure 18.3 shows the status change of the Ether-C transmitter. This operation is the
same between ports 0 and 1. The priority of the process when transmit frame from E-DMAC and
relay frame transmission collide can be set by the Transmit/Relay Priority Control Mode register
(TSU_PRISL0/1).
Rev. 2.00 Dec. 07, 2005 Page 707 of 950
REJ09B0079-0200