SH7710 Datasheet, PDF (296/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
8.4.7 Interrupt Request Register 3 (IRR3)
IRR3 is an 8-bit register that indicates whether interrupt requests from the RTC are generated.
This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in
standby mode.
Bit
7 to 3
Bit Name

2
CUIR
1
PRIR
0
ATIR
Initial Value R/W
All 0
R
0
R
0
R
0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
CUI Interrupt Request
Indicates whether the CUI (RTC) interrupt
request is generated.
0: CUI interrupt request is not generated
1: CUI interrupt request is generated
PRI Interrupt Request
Indicates whether the PRI (RTC) interrupt
request is generated.
0: PRI interrupt request is not generated
1: PRI interrupt request is generated
ATI Interrupt Request
Indicates whether the ATI (RTC) interrupt
request is generated.
0: ATI interrupt request is not generated
1: ATI interrupt request is generated
Rev. 2.00 Dec. 07, 2005 Page 254 of 950
REJ09B0079-0200