SH7710 Datasheet, PDF (180/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
3.5.12 Local Data Move Instruction
The DSP unit of this LSI provides additional two independent registers, MACL and MACH, in
order to support CPU standard multiply/MAC operations. They can be also used as temporary
storage registers by local data move instructions between MACH/L and other DSP registers.
Figure 3.22 shows the flow of seven local data move instructions. Table 3.33 shows the variation
of this type of instruction.
PSTS
X0
Y0
M0
A0
MACH
MACL
PLDS
X1
Y1
M1
A1
A0G A1G
DSR
Cannot be used
Figure 3.22 Local Data Move Instruction Flow
Table 3.33 Variation of Local Data Move Operations
Mnemonic
PLDS
PSTS
Function
Data move from DSP register to MACL/MACH
Data move from MACL/MACH to DSP register
Operand
Dz
Dz
This instruction is very similar to other transfer instructions. If either the A0 or A1 register is
specified as the destination operand of PSTS, the signed bit is sign-extended and copied into the
corresponding guard-bit parts, A0G or A1G. The DC bit in DSR and other condition code bits are
not updated regardless of the instruction result. This instruction can operate as a conditional. This
instruction can operate with MOVX and MOVY in parallel.
Rev. 2.00 Dec. 07, 2005 Page 138 of 950
REJ09B0079-0200