SH7710 Datasheet, PDF (718/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
Initial
Bit
Bit Name Value R/W Description
26
TINTM30 0
R/W MAC-0 Carrier Lost Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
25
TINTM20 0
R/W MAC-0 Collision Detect Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
24
TINTM10 0
R/W MAC-0 Transmission Time Out Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
23
OVFM0 0
R/W Port 0 to 1 TSU FIFO Overflow Detect Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
22
RBSYM0 0
R/W MAC-0 Overflow Alert Signal Output Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
21

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
20
RINTM50 0
R/W MAC-0 Residual Bit Frame Receive Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
19
RINTM40 0
R/W MAC-0 Exceeding Byte Frame Receive Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
18
RINTM30 0
R/W MAC-0 Less 64-Byte Frame Receive Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
17
RINTM20 0
R/W MAC-0 Frame Receive Error Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
Rev. 2.00 Dec. 07, 2005 Page 676 of 950
REJ09B0079-0200