SH7710 Datasheet, PDF (700/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.21 TSU Counter Reset Register (TSU_CTRST)
TSU_CTRST clears the transmit, receive, and transfer frame counters to 0.
Initial
Bit
Bit Name Value R/W Description
31 to 9 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
8
CTRST 0
R/W TSU Counter Reset
When 1 is written to this bit, the values of registers
TXNCR0/1, TXALCR0/1, RXNLCR0/1, RXALCR0/1,
FWNLCR0/1, and FWALCR0/1 are cleared to 0. Writing
0 does not affect this bit. These bits are always read as
0.
7 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
18.3.22 Relay Enable Register (Port 0 to 1) (TSU_FWEN0)
TSU_FWEN0 enables or disables relay operations from the MAC-0 to MAC-1 (writing to the
relay FIFO).
Initial
Bit
Bit Name Value R/W Description
31
FWEN0 0
R/W Port 0 to 1 Relay Operation Enable
0: Port 0 to 1 relay is disabled
1: Port 0 to 1 relay is enabled
When the value of the FCM2 to FCM0 in the TSU FIFO
size select register TSU_FCM is set to H′4, setting this
bit to 1 is prohibited.
30 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Dec. 07, 2005 Page 658 of 950
REJ09B0079-0200