SH7710 Datasheet, PDF (483/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
CKIO
A25 to A0
T1 Tw Tw TB2 Twb TB2 Twb TB2 Twb T2
CS
RD/WR
RD
D31 to D0
WAIT
BS
DACK
Figure 12.32 Burst ROM (Clock Asynchronous) Access (Bus Width = 32 Bits,
16-byte Transfer (Number of Bursts = 4), Access Wait for First Time = 2,
Access Wait for 2nd Time and after = 1)
12.5.7 Byte-Selection SRAM Interface
The byte-selection SRAM interface is for access to an SRAM which has a byte-selection pin
(WEn (BEn)). This interface has 16-bit data pins and accesses SRAMs having upper and lower
byte selection pins, such as UB and LB.
When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the byte-
selection SRAM interface is the same as that for the normal space interface. While in read access
of a byte-selection SRAM interface, the byte-selection signal is output from the WEn (BEn) pin,
which is different from that for the normal space interface. The basic access timing is shown in
figure 12.33. In write access, data is written to the memory according to the timing of the byte-
selection pin (WEn (BEn)). For details, refer to the data sheet for the corresponding memory.
If the BAS bit in CSnWCR is set to 1, the WEn (BEn) pin and RD/WR pin timings change. Figure
12.34 shows the basic access timing. In write access, data is written to the memory according to
the timing of the write enable pin (RD/WR). The data hold timing from RD/WR negation to data
write must be acquired by setting the HW[1:0] bits in CSnWCR. Figure 12.35 shows the access
timing when a software wait is specified.
Rev. 2.00 Dec. 07, 2005 Page 441 of 950
REJ09B0079-0200