SH7710 Datasheet, PDF (971/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Main Revisions and Additions in this Edition
Item
Section 1 Overview and Pin
Function
1.1 Features
1.2 Block Diagram
Figure 1.1 Block Diagram
Page Revision (See Manual for Details)
4
Realtime clock (RTC)*¹
5
• Detects short frames and long frames
• Conforms to MII (Media Independent Interface)
standard *²
:
• WOL (Wake-On-LAN) signal output with Magic
Packet*³ detection
6
Notes: 1. As the power supply is connected,
power should always be supplied to all
power supplies even if only RTC operates.
2. +5 V I/O is not supported.
3. Magic Packet is the registered trademark of
Advanced Micro Devices Inc.
Product Lineup added
7
Advanced
SuperH
CPU core
DSP core
User break
controller
user
debugger
(UBC)
(AUD)
L bus
CPU bus (I clock)
X/Y memory
Instructions/data for
CPU/DSP 16 kbytes
X bus
Y bus
Cache
access
controller
(CCN)
Internal bus (B clock)
Cache
memory
32 kbytes
Memory
management
unit
(MMU)
1.3 Pin Description
1.3.1 Pin Assignment
8, 9 HQFP2828-256 (FP-256G/GV)
Figure 1.3 Pin Assignment (P-LFBGA1717-256 (BP-
256H/HV)) added
Rev. 2.00 Dec. 07, 2005 Page 929 of 950
REJ09B0079-0200