SH7710 Datasheet, PDF (727/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
Initial
Bit
Bit Name Value R/W Description
8
TEN23 0
R/W CAM Entry Table 23 (TSU_ADRH23 and TSU_ADRL23)
Setting
0: Disabled
1: Enabled
7
TEN24 0
R/W CAM Entry Table 24 (TSU_ADRH24 and TSU_ADRL24)
Setting
0: Disabled
1: Enabled
6
TEN25 0
R/W CAM Entry Table 25 (TSU_ADRH20 and TSU_ADRL25)
Setting
0: Disabled
1: Enabled
5
TEN26 0
R/W CAM Entry Table 26 (TSU_ADRH20 and TSU_ADRL26)
Setting
0: Disabled
1: Enabled
4
TEN27 0
R/W CAM Entry Table 27 (TSU_ADRH27 and TSU_ADRL27)
Setting
0: Disabled
1: Enabled
3
TEN28 0
R/W CAM Entry Table 28 (TSU_ADRH28 and TSU_ADRL28)
Setting
0: Disabled
1: Enabled
2
TEN29 0
R/W CAM Entry Table 29 (TSU_ADRH29 and TSU_ADRL29)
Setting
0: Disabled
1: Enabled
1
TEN30 0
R/W CAM Entry Table 30 (TSU_ADRH30 and TSU_ADRL30)
Setting
0: Disabled
1: Enabled
Rev. 2.00 Dec. 07, 2005 Page 685 of 950
REJ09B0079-0200