SH7710 Datasheet, PDF (638/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Bit
11
10
9
8
7
6 to 4
3
2
1
0
Initial
Bit Name Value R/W
RDLA3 0
R/W
RDLA2 0
R/W
RDLA1 0
R/W
RDLA0 0
R/W
RDRE 0
R/W
—
All 0 R
RDRA3 0
R/W
RDRA2 0
R/W
RDRA1 0
R/W
RDRA0 0
R/W
Description
Receive Left Channel Data Assigns 3 to 0
Specify the position of left-channel data in a receive
frame as B′0000 to B′1110. Receive data for the left
channel is stored in bits SIRDL15 to SIRDL0 in SIRDR.
Note: If the RDLA3 to RDLA0 bits are set to B′1111,
operation is not guaranteed.
Receive Right Channel Data Enable
0: Disables right channel data reception
1: Enables right channel data reception
Reserved
These bits are always read as 0. The write value should
always be 0.
Receive Right Channel Data Assigns 3 to 0
Specify the position of right-channel data in a receive
frame as B′0000 to B′1110. Receive data for the right
channel is stored in bits SIRDR15 to SIRDR0 in SIRDR.
Note: If the RDRA3 to RDRA0 bits are set to B′1111,
operation is not guaranteed.
17.3.5 Serial Control Data Assign Register (SICDAR)
SICDAR is used to specify the position of the control data in a frame. SICDAR can be specified
only when the FL3 to FL0 bits in SIMDR are specified as 1xxx. SICDAR is initialized by a
power-on reset or software reset.
Initial
Bit
Bit Name Value R/W Description
15
CD0E
0
R/W Control Channel 0 Data Enable
0: Disables transmission and reception of control channel
0 data
1: Enables transmission and reception of control channel
0 data
14 to 12 —
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Dec. 07, 2005 Page 596 of 950
REJ09B0079-0200