SH7710 Datasheet, PDF (93/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Instruction Format
Source
Operand
Destination
Operand
Sample Instruction
i type
15
0
xxxx xxxx i i i i i i i i
iiiiiiii: immediate
Indexed GBR
indirect
AND.B
#imm,@(R0,GBR)
ni type
15
0
xxxx nnnn i i i i i i i i
iiiiiiii: immediate
iiiiiiii: immediate
iiiiiiii: immediate
R0 (register direct) AND #imm,R0
—
TRAPA #imm
nnnn: register
direct
ADD #imm,Rn
Note: * In multiply-and-accumulate instructions, nnnn is the source register.
Rev. 2.00 Dec. 07, 2005 Page 51 of 950
REJ09B0079-0200