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SH7710 Datasheet, PDF (682/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Section 18 Ethernet Controller (EtherC)
Name
Port Abbreviation I/O Function
Transmit enable 1
TX-EN1*1
O
Indicates that transmit data is ready on
ETXD3 to ETXD0
Transmit data
1
ETXD13 to O
ETXD10*1
4-bit transmit data
Transmit error
1
TX-ER1*1
O
Notifies PHY-LSI of error during
transmission
Receive data valid 1
RX-DV1*1 I
Indicates that valid receive data is on
ERXD3 to ERXD0
Receive data
1
ERXD13 to I
ERXD10*1
4-bit receive data
Receive error
1
RX-ER1*1 I
Identifies error state occurred during data
reception
Carrier detection 1
CRS1*1
I
Carrier detection signal
Collision detection 1
COL1*1
I
Collision detection signal
Management data 1
clock
MDC1*1
O Reference clock signal for information
transfer via MDIO
Management data 1
I/O
MDIO1*1
I/O Bidirectional signal for exchange of
management information between this LSI
and PHY
Link status
1
LKNSTA1 I
Inputs link status from PHY
General-purpose 1
external output
EXOUT1
O
Signal indicating value of register-bit
(ECMR1-ELB)
Wake-On-LAN
1
WOL1
O Signal indicating reception of Magic Packet
CAM input 0

CAMSEN0*2 I
CAM interface signal input 0
CAM input 1

CAMSEN1*2 I
CAM interface signal input 1
Bus release request 
ARBUSY*3 O
Signal indicating bus release request when
the threshold value set for the data volume
in the receive FIFO has been exceeded
Notes: 1. MII signal conforming to IEEE802.3u
2. The CAM input signal function is set by the CAMSEL03 to CAMSEL00 and CAMSEL13
to CAMSEL10 in the TSU_FWSLC register.
3. Refer to section 19, Ethernet Controller Direct Memory Access Controller (E-DMAC)
and section 19.2.18, Overflow Alert FIFO Threshold Register (FCFTR).
Rev. 2.00 Dec. 07, 2005 Page 640 of 950
REJ09B0079-0200