SH7710 Datasheet, PDF (697/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.14 CRC Error Frame Receive Counter Register (CEFCR)
CEFCR is a 32-bit counter that indicates the number of times a frame with a CRC error was
received. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter
value is cleared to 0 by a write to this register with any value.
Initial
Bit
Bit Name Value
31 to 0 CEFC31 to All 0
CEFC0
R/W Description
R/W CRC Error Frame Count
These bits indicate the count of CRC error frames
received.
18.3.15 Frame Receive Error Counter Register (FRECR)
FRECR is a 32-bit counter that indicates the number of frames for which a receive error was
indicated by the RX-ER input pin from the PHY-LSI. FRECR is incremented each time the RX-
ER pin becomes active. When the value in this register reaches H'FFFFFFFF, the count is halted.
The counter value is cleared to 0 by a write to this register with any value.
Initial
Bit
Bit Name Value
31 to 0 FREC31 to All 0
FREC0
R/W Description
R/W Frame Receive Error Count
These bits indicate the count of errors during frame
reception.
18.3.16 Too-Short Frame Receive Counter Register (TSFRCR)
TSFRCR is a 32-bit counter that indicates the number of frames of fewer than 64 bytes that have
been received. When the value in this register reaches H'FFFFFFFF, the count is halted. The
counter value is cleared to 0 by a write to this register with any value.
Initial
Bit
Bit Name Value
31 to 0 TSFC31 to All 0
TSFC0
R/W Description
R/W Too-Short Frame Receive Count
These bits indicate the count of frames received with a
length of less than 64 bytes.
Rev. 2.00 Dec. 07, 2005 Page 655 of 950
REJ09B0079-0200