SH7710 Datasheet, PDF (47/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 1 Overview and Pin Function
Serial communication interface with FIFO (SCIF):
• 16 bytes each for transmit/receive FIFO
• Two channels (SCIF0 and SCIF1)
• CTS/RTS (flow control) support
• Asynchronous and synchronous modes
• Full-duplex communication support
• DMA transfer
Serial I/O with FIFO (SIOF):
• 64 bytes each for transmit/receive FIFO
• 8-/16-/16-bit stereo-audio input/output supported
• Two channels (SIOF0 and SIOF1)
• DMA transfer
• Frame synchronous signal
Ethernet controller (EtherC):
• MAC (Media Access Control)
• Data frame assembly/disassembly (frame format conforming to IEEE802.3u)
• CSMA/CD link management (collision prevention and collision processing)
• CRC processing
• Full-duplex transmit/receive support
• Detects short frames and long frames
• Conforms to MII (Media Independent Interface) standard *²
• Conversion from 8-bit stream data in MAC layer to MII nibble (4-bit) stream
• Station management (STA function)
• 10/100 Mbps transfer rate adjustable
• WOL (Wake-On-LAN) signal output with Magic Packet*³ detection
• CAM sense signal input
Ethernet Controller Direct Memory Access Controller (E-DMAC):
• EtherC  Transfer between external and internal memories
• 16-byte burst transfer
• Single address transfer
• Chain block transfer
Rev. 2.00 Dec. 07, 2005 Page 5 of 950
REJ09B0079-0200