SH7710 Datasheet, PDF (29/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Figure 10.7 STATUS Output when Sleep Mode is Canceled by Interrupt................................. 309
Figure 10.8 STATUS Output when Sleep Mode is Canceled by Power-on Reset...................... 309
Figure 10.9 STATUS Output when Sleep Mode is Canceled by Manual Reset......................... 310
Section 11 On-Chip Oscillation Circuits
Figure 11.1 Block Diagram of CPG ........................................................................................... 313
Figure 11.2 Block Diagram of WDT .......................................................................................... 323
Figure 11.3 Writing to WTCNT and WTCSR............................................................................ 327
Figure 11.4 Points for Attention when Using Crystal Resonator................................................ 329
Figure 11.5 Points for Attention when Using PLL Oscillator Circuit ........................................ 330
Section 12 Bus State Controller (BSC)
Figure 12.1 Block Diagram of BSC............................................................................................ 333
Figure 12.2 Address Space ......................................................................................................... 337
Figure 12.3 Normal Space Basic Access Timing (Access Wait 0)............................................. 389
Figure 12.4 Continuous Access for Normal Space 1, Bus Width = 16 bits, Longword Access,
CSnWCR.WM Bit = 0 (Access Wait = 0, Cycle Wait = 0)..................................... 391
Figure 12.5 Continuous Access for Normal Space 2, Bus Width = 16 bits, Longword Access,
CSnWCR.WM Bit = 1 (Access Wait = 0, Cycle Wait = 0)..................................... 392
Figure 12.6 Example of 32-Bit Data-Width SRAM Connection ................................................ 393
Figure 12.7 Example of 16-Bit Data-Width SRAM Connection ................................................ 394
Figure 12.8 Example of 8-Bit Data-Width SRAM Connection .................................................. 394
Figure 12.9 Wait Timing for Normal Space Access (Software Wait Only) ............................... 395
Figure 12.10 Wait State Timing for Normal Space Access
(Wait State Insertion by WAIT Signal)................................................................. 396
Figure 12.11 CSn Assert Period Expansion................................................................................ 397
Figure 12.12 Example of 32-Bit Data-Width SDRAM Connection ........................................... 399
Figure 12.13 Example of 16-Bit Data-Width SDRAM Connection ........................................... 400
Figure 12.14 Burst Read Basic Timing (Auto Precharge) .......................................................... 415
Figure 12.15 Burst Read Wait Specification Timing (Auto Precharge) ..................................... 416
Figure 12.16 Basic Timing for Single Read (Auto Precharge)................................................... 417
Figure 12.17 Basic Timing for Burst Write (Auto Precharge).................................................... 419
Figure 12.18 Basic Timing for Single Write (Auto-Precharge).................................................. 420
Figure 12.19 Burst Read Timing (No Auto Precharge) .............................................................. 422
Figure 12.20 Burst Read Timing (Bank Active, Same Row Address) ....................................... 423
Figure 12.21 Burst Read Timing (Bank Active, Different Row Addresses) .............................. 424
Figure 12.22 Single Write Timing (No Auto Precharge)............................................................ 425
Figure 12.23 Single Write Timing (Bank Active, Same Row Address) ..................................... 426
Figure 12.24 Single Write Timing (Bank Active, Different Row Addresses) ............................ 427
Figure 12.25 Auto-Refresh Timing ............................................................................................ 429
Figure 12.26 Self-Refresh Timing .............................................................................................. 431
Rev. 2.00 Dec. 07, 2005 Page xxix of xlii