SH7710 Datasheet, PDF (756/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
shows the connection example of the external CAM logic while figure 18.6 shows the timing
conditions of the external CAM signal.
This LSI
EtherC
MII (RX-DV, RXD3 to RXD0)
PHY-LSI
External memory
Descriptor
CAMSEN0 or
CAMSEN1 pin
External
CAM logic
Figure 18.5 Example of External CAM Connection
The setting on whether to enable or disable the referencing of external CAM logic evaluation
results by the CAMSEN0 and CAMSEN1 pins is carried out by the transfer function setting
register (common) (TSU_FWSLC). When referencing of the CAMSEN0 and CAMSEN1 pins is
enabled during receive, it is determined whether to send or discard the frames input from to MAC-
0/1 to E-DMAC0/1 (have E-DMAC receive the frames) according to the value of the CAMSEN0
or CAMSEN1 pin. When relaying and CAMSEN0/1 pin referencing are enabled at the same time,
the transfer or discard of multicast frames and frames to destinations other than this LSI can be
determined by the value of the CAMSEN0 and CAMSEN1 pins.
Table 18.5 shows the processing method (receive or discard) for frames in MAC0 to E-DMAC0 or
MAC1 to E-DMAC1 reception, while Table 18.6 shows the processing method (receive or
discard) for frames in MAC0 to MAC1 or MAC1 to MAC relay. The external CAM logic is
memorized with MAC addresses different from the CAM entry table in this LSI. When the MAC
address received from the PHY matches the destination address memorized in the external CAM
logic, the CAMSEN0 or CAMSEN1 pin is asserted*. EtherC receives or discards the frames when
CAMSEN0/1 was asserted according to the settings in table 18.5.
Figure 18.6 shows the valid range of CAMSEN0/1 assertion for the corresponding receive frames.
Rev. 2.00 Dec. 07, 2005 Page 714 of 950
REJ09B0079-0200