SH7710 Datasheet, PDF (724/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.39 CAM Entry Table Enable Register (TSU_TEN)
TSU_TEN enables or disables to refer CAM Entry Table registers (TSU_ADRH0 to
TSU_ADRH31 and TSU_ADRL0 to TSU_ADRL31).
Initial
Bit
Bit Name Value R/W Description
31
TEN0
0
R/W CAM Entry Table 0 (TSU_ADRH0 and TSU_ADRL0)
Setting
0: Disabled
1: Enabled
30
TEN1
0
R/W CAM Entry Table 1 (TSU_ADRH1 and TSU_ADRL1)
Setting
0: Disabled
1: Enabled
29
TEN2
0
R/W CAM Entry Table 2 (TSU_ADRH2 and TSU_ADRL2)
Setting
0: Disabled
1: Enabled
28
TEN3
0
R/W CAM Entry Table 3 (TSU_ADRH3 and TSU_ADRL3)
Setting
0: Disabled
1: Enabled
27
TEN4
0
R/W CAM Entry Table 4 (TSU_ADRH4 and TSU_ADRL4)
Setting
0: Disabled
1: Enabled
26
TEN5
0
R/W CAM Entry Table 5 (TSU_ADRH5 and TSU_ADRL5)
Setting
0: Disabled
1: Enabled
25
TEN6
0
R/W CAM Entry Table 6 (TSU_ADRH6 and TSU_ADRL6)
Setting
0: Disabled
1: Enabled
Rev. 2.00 Dec. 07, 2005 Page 682 of 950
REJ09B0079-0200