SH7710 Datasheet, PDF (262/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 6 Cache
Table 6.2 Way Replacement when a PREF Instruction Misses the Cache
DSP Bit W3LOAD W3LOCK W2LOAD W2LOCK Way to be Replaced
0
*
*
*
*
Determined by LRU (table 6.1)
1
*
0
*
0
Determined by LRU (table 6.1)
1
*
0
0
1
Determined by LRU (table 6.4)
1
0
1
*
0
Determined by LRU (table 6.5)
1
0
1
0
1
Determined by LRU (table 6.6)
1
0
*
1
1
Way 2
1
1
1
0
*
Way 3
Note: * Don't care
W3LOAD and W2LOAD should not be set to 1 at the same time.
Table 6.3 Way Replacement when Instructions other than the PREF Instruction Miss the
Cache
DSP Bit W3LOAD W3LOCK W2LOAD W2LOCK Way to be Replaced
0
*
*
*
*
Determined by LRU (table 6.1)
1
*
0
*
0
Determined by LRU (table 6.1)
1
*
0
*
1
Determined by LRU (table 6.4)
1
*
1
*
0
Determined by LRU (table 6.5)
1
*
1
*
1
Determined by LRU (table 6.6)
Note: * Don't care
W3LOAD and W2LOAD should not be set to 1 at the same time.
Table 6.4 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =0)
LRU (Bits 5 to 0)
000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100
000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111
101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111
Way to be Replaced
3
1
0
Rev. 2.00 Dec. 07, 2005 Page 220 of 950
REJ09B0079-0200