SH7710 Datasheet, PDF (703/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.25 Relay FIFO Overflow Alert Set Register (Port 0) (TSU_BSYSL0)
The TSU has an alert function, which informs the MAC-0 and MAC-1 that writing to the TSU
FIFO will be disabled when the data volume written in the TSU FIFO during relay operations
exceeds a certain threshold. TSU_BSYSL0 sets the threshold of the TSU FIFO when the TSU
alerts the MAC-0 that writing to the TSU FIFO will be disabled during relay operations.
Bit
Bit Name
31 to 6 
Initial
Value
All 0
5 to 0 BSYSL05 to All 1
BSYSL00
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Sets the threshold of the port 0 to 1 TSU FIFO
capacity in 256-byte units when the TSU alerts the
MAC-0 that writing in the TSU FIFO will be disabled
during relay operations.
H′00: 0 byte
H′01: 256 bytes
H′02: 512 bytes
:
:
H′16: 5632 bytes
H′17: 5888 bytes
Settings are disabled for H′18 to H′3F. (Alert is not
always carried out.)
When H′00 is set, the TSU always alerts the MAC-0
that writing to the TSU FIFO will be disabled. When
the value set is above the port 0 to 1 transfer FIFO
capacity set by the FCM2 to FCM0 in TSU_FCM, the
TSU does not alert the MAC-0 that writing to the TSU
FIFO will be disabled.
Writing to this register is prohibited, after relay
operations have been enabled once (after the
FWEN0 in TSU_FWEN0 or the FWEN1 in
TSU_FWEN1 is set to 1).
When the enable bit of relay operations (the FWEN0
in TSU_FWEN0 or the FWEN1 in TSU_FWEN1) is
cleared to 0, the TSU stops alerting the MAC-0 that
writing to the TSU FIFO will be disabled.
Rev. 2.00 Dec. 07, 2005 Page 661 of 950
REJ09B0079-0200