SH7710 Datasheet, PDF (411/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
11
TRCD1 0
10
TRCD0 1
R/W Number of Wait Cycles from ACTV Command to
R/W ^{READ (A)/WRIT (A) Command}
Specify the number of minimum wait cycles from issuing
the ACTV command to issuing the READ (A)/WRIT (A)
command. The setting for areas 2 and 3 is common.
00: 0 cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
9

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
8
A3CL1 1
R/W CAS Latency for Area 3.
7
A3CL0 0
R/W Specify the CAS latency for area 3.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
6, 5 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Dec. 07, 2005 Page 369 of 950
REJ09B0079-0200