SH7710 Datasheet, PDF (422/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
12.4.5 Refresh Timer Control/Status Register (RTCSR)
RTCSR specifies various items about refresh for SDRAM.
When RTCSR is written, the upper 16 bits of the write data must be H’A55A to cancel write
protection.
Initial
Bit
Bit Name Value R/W
31 to 8 
All 0 R
7
CMF
0
R/W
6
CMIE
0
R/W
5
CKS2
0
R/W
4
CKS1
0
R/W
3
CKS0
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Compare Match Flag
Indicates that a compare match occurs between the refresh
timer counter (RTCNT) and refresh time constant register
(RTCOR). This bit is set or cleared in the following
conditions.
0: Clearing condition: When 0 is written in CMF after
reading out RTCSR during CMF = 1.
1: Setting condition: When the condition RTCNT = RTCOR
is satisfied.
Compare Match Interrupt Enable
Enables or disables a CMF interrupt request when the CMF
bit of RTCSR is set to 1.
0: Disables the CMF interrupt request
1: Enables the CMF interrupt request
Clock Select
Select the clock input to count-up the refresh timer counter
(RTCNT).
000: Stop the counting-up
001: Bφ/4
010: Bφ/16
011: Bφ/64
100: Bφ/256
101: Bφ/1024
110: Bφ/2048
111: Bφ/4096
Rev. 2.00 Dec. 07, 2005 Page 380 of 950
REJ09B0079-0200