SH7710 Datasheet, PDF (731/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.41 CAM Entry Table POST2 Register (TSU_POST2)
When using the CAM, the conditions for referring to each CAM entry table can be specified by
using the TSU_POST1 to TSU_POST4 registers. TSU_POST2 specifies the conditions for
referring to TSU_ADRH8 to TSU_ADRH15 and TSU_ADRL8 to TSU_ADRL15. The settings of
this register are valid when the POSENU bit in TSU_FWSLC is set to 1.
Initial
Bit
Bit Name Value R/W Description
31 to 28 POST83 to All 0
POST80
R/W These bits set the conditions for referring to the CAM
entry table 8. By setting multiple bits to 1, multiple
conditions can be selected.
POST83: The CAM entry table 8 is referred in port 0
reception.
POST82: The CAM entry table 8 is referred in port 0
to 1 relay.
POST81: The CAM entry table 8 is referred in port 1
reception.
POST80: The CAM entry table 8 is referred in port 1
to 0 relay.
27 to 24 POST93 to All 0
POST90
R/W These bits set the conditions for referring to the CAM
entry table 9. By setting multiple bits to 1, multiple
conditions can be selected.
POST93: The CAM entry table 9 is referred in port 0
reception.
POST92: The CAM entry table 9 is referred in port 0
to 1 relay.
POST91: The CAM entry table 9 is referred in port 1
reception.
POST90: The CAM entry table 9 is referred in port 1
to 0 relay.
Rev. 2.00 Dec. 07, 2005 Page 689 of 950
REJ09B0079-0200