SH7710 Datasheet, PDF (239/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 5 Memory Management Unit (MMU)
registered in index mode. When memory is shared by several processings, different pages must
be registered in each ASID.
The object compared varies depending on the page management information (SZ, SH) in the TLB
entry. It also varies depending on whether the system supports multiple virtual memory or single
virtual memory.
The page-size information determines whether VPN (11 to 10) is compared. VPN (11 to 10) is
compared for 1-kbyte pages (SZ = 0) but not for 4-kbyte pages (SZ = 1).
The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry
are compared. ASIDs are compared when there is no sharing between processes (SH = 0) but not
when there is sharing (SH = 1).
When single virtual memory is supported (MMUCR.SV = 1) and privileged mode is engaged
(SR.MD = 1), all process resources can be accessed. This means that ASIDs are not compared
when single virtual memory is supported and privileged mode is engaged. The objects of address
comparison are shown in figure 5.10.
SH = 1 or
No
(SR.MD = 1 and
MMUCR.SV = 1)?
Yes
SZ = 0?
No (4-kbyte)
SZ = 0?
No (4-kbyte)
Yes (1-kbyte)
Yes (1-kbyte)
Bits Compared:
VPN 31 to 17
VPN 11 to 10
Bits Compared:
VPN 31 to 17
Bits Compared:
VPN 31 to 17
VPN 11 to 10
ASID 7 to 0
Bits Compared:
VPN 31 to 17
ASID 7 to 0
Figure 5.10 Objects of Address Comparison
Rev. 2.00 Dec. 07, 2005 Page 197 of 950
REJ09B0079-0200